`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:17:00 11/05/2013 
// Design Name: 
// Module Name:    Transmisor 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Transmisor
	#(
	 parameter D_BITS = 8,
				  CANT_TICKS = 16)
(
    input clock,
    input reset,
    input s_tick,
    input [7:0] data_input,
    input tx_start,
    output tx_done,
    output data_output
    );

localparam IDLE = 2'b00,
			  START = 2'b01,
			  DATA = 2'b10,
			  STOP = 2'b11;

reg [4:0] tick_counter;
reg [3:0] number_bits; // n, cuenta kla cantidad de  bits que se van enviando
reg [7:0] shift_register; // almacena el dato de 8 bits a enviar
reg [1:0] next_state, current_state; 
reg dato_salida;


// Logica de Memoria
always @(negedge clock, negedge reset)
	begin
		if(~reset)
			current_state <= IDLE;
		else
			current_state <= next_state;
	end
	
// Logica de cambio de estado
always @*
	begin
		tx_done = 1'b0;
		
		case(current_state)
			IDLE:
				begin
					if(tx_start == 1)
						begin
							next_state = START;
							tick_counter = 0;
							shift_register = data_input ;
						end
				end
			START:
				begin
					if(s_tick == 1)
						begin
							if(tick_counter < 16)
								tick_counter = tick_counter +1;
							else
								begin
									tick_counter = 0;
									number_bits = 0;
									next_state = DATA;
								end
						end
				end
			DATA:
				begin
					if(s_tick == 1)
						begin
							if(tick_counter == CANT_TICKS-1)
								begin
									tick_counter = 0;
									datos_salida = shift_register[7-number_bits];
									if(number_bits == D_BITS-1)
										begin
											next_state = STOP;
										end
									else
										begin
											number_bits = number_bits +1;
										end
								end
							else
								begin
									tick_counter = tick_counter + 1;
								end
						end
				end
			STOP:
				begin
					if(s_tick == 1)
						begin
							if(tick_counter == CANT_TICKS-1)
								begin
									tx_done = 1'b1;
									next_state = IDLE;
								end
							else
								tick_counter = tick_counter + 1;
						end
				end
		endcase
	end




endmodule
